BACKSIDE BUS

In computer microprocessor architecture, a 'backside bus' is a bus dedicated to the purpose of connecting the processor to an off-chip bank of cache memory. This is an improvement over the older practice of accessing the cache over the frontside bus (FSB) because it reduces the usage of the FSB, which is typically a severe bottleneck in most modern systems. In addition, due to its dedicated nature, the backside bus can be optimized or customized to the single task of communicating with the backside cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose FSB. Furthermore, since the backside bus operates over a shorter distance, it can typically operate at higher clock speeds, allowing higher bandwidth access to the cache. If the backside bus is to an on-chip backside cache, the interface can also be made much wider (256-bit, 512-bit) than is feasible via an off-chip or even on-chip FSB interface.
This architecture has been used in a number of chips, including the Intel Pentium Pro and Pentium II processors (which used it for access to their L2 cache; earlier processors had accessed the L2 cache over the FSB, while later processors moved it on-chip) and IBM and Freescale PowerPC processors (the G3 line, certain PowerPC 604 models, and the Freescale G4 line).

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External links

References

★ Monday a big day for Apple

★ Buses: frontside and backside

External links

★ Backside Bus at Whatis.com

★ Dedicated Backside Cache Bus at PCGuide.Com