DDR SDRAM

'DDR SDRAM' or 'double-data-rate synchronous dynamic random access memory' is a class of memory integrated circuit used in computers. It achieves greater bandwidth than the preceding single-data-rate SDRAM by transferring data on the rising and falling edges of the clock signal (double pumped). Effectively, it nearly doubles the transfer rate without increasing the frequency of the front side bus.
Thus, a system with a 100 MHz front side bus has an effective clock rate of 200 MHz when DDR SDRAM memory is installed. The same system using SDR (single data rate) SDRAM, will not have its front side bus rate doubled and be limited to a 100 MHz front side bus speed.
With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of [mbcr x 2 x 64] / 8; annotated it looks like this: (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s.
JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules.
As DDR is superseded by the newer DDR2, the older version is often now referred to as 'DDR1'.

Contents

Chips and modules

Chip characteristics

Module characteristics

Alternatives

MDDR

See also

External links

Chips and modules

Standard name	Memory clock	Time between signals	I/O Bus clock	Data transfers per second	Module name	Peak transfer rate
DDR-200	100 MHz	10 ns	100 MHz	200 Million	PC-1600	1.600 GB/s
DDR-266	133 MHz	7.5 ns	133 MHz	266 Million	PC-2100	2.133 GB/s
DDR-333	166 MHz	6 ns	166 MHz	333 Million	PC-2700	2.667 GB/s
DDR-400	200 MHz	5 ns	200 MHz	400 Million	PC-3200	3.200 GB/s

'Note:' All above listed are specified by JEDEC as JESD79. All RAM speeds in-between or above these listed specifications are not standardized by JEDEC — most often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.
The package sizes in which DDR SDRAM is manufactured are also standardised by JEDEC.


There is no architectural difference between DDR SDRAM designed for different clock frequencies, e.g. PC-1600 (designed to run at 100 MHz) and PC-2100 (designed to run at 133 MHz). The number simply designates the speed that the chip is guaranteed to run at. Hence DDR SDRAM can be run at lower clock speeds than it was made for (underclocking) or higher clock speeds than it was made for (overclocking).
DDR SDRAM DIMMs have 184 pins (as opposed to 168 pins on SDRAM, or, 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power usage. Note: some DIMMs have nominal voltage of 2.6 V [1].
Many new chipsets use these memory types in dual-channel configurations, which doubles or quadruples the effective bandwidth.

Chip characteristics

★ 'DRAM density'. Size of the chip in mebibits. Example: 256 Mibit — 32 MiB chip.

★ 'DRAM organization'. Written in the form of 64M x 4, where 64M is a number of storage units (64 million), x4 (pronounced «by 4») — number of bits per chip, which equals the number of bits per storage unit. There are x4, x8, and x16 DDR chips. The x4 chips allows the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC, while the x8 and x16 chips are somewhat more expensive.

Module characteristics

★ Size.

★ '# of DRAM Devices'. The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (Single Sided) or both sides (Dual Sided) of the module. The maximum amount of chips per DDR module is 36 (9x4).

★ '# of DRAM rows (ranks)'. Any given module can have 1, 2 or 4 rows, but only 1 row of a module can be active at any moment of time. When a module has 2 or more rows, the memory controller must periodically switch between them by performing close and open operations.

★ 'Timings': CAS Latency (CL), Clock Cycle Time (tCK), Row Cycle Time (tRC), Refresh Row Cycle Time (tRFC), Row Active Time (tRAS).

★ 'Buffering': Registered vs. unbuffered
Module and chip characteristics are inherently linked.
Total module size is a product of one chip size by number of chips. ECC modules multiply it by 8/9 because they use one bit per every byte for error correction. A module of any particular size can therefore be assembled either from 36 small chips, or 18 or 9 bigger ones.
DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using x8 chips instead of x4 will have more ranks.

'Example: Variations of 1 GiB PC2100 Registered DDR SDRAM module'

Module size	Number of chips	Chip size	Chip organization	Number of rows (ranks)
1 GiB	36	256 Mibit	64M x 4	2
1 GiB	18	512 Mibit	64M x 8	2
1 GiB	18	512 Mibit	128M x 4	1

This example compares different real-world server memory modules with a common size of 1 GiB. One should definitely be careful buying 1 GiB memory module, because all these variations can be sold under one price position without stating whether they are x4 or x8, single or dual ranked.
There is a common belief that number of module rows or ranks equals number of sides. As above data shows, this is not true. One can find (2-side, 1-rank) or (2-side, 4-rank) modules. One can even think of 1-side, 2-rank memory module having 16(18) chips on single side x8 each, but it's unlikely such a module was ever produced.

Alternatives

DDR (DDR1) has been superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR DRAM. DDR2 has become the standard, as XDR is lacking support. DDR3 SDRAM is a new standard that offers even faster performance and new features.
DDR's prefetch buffer depth is 2 bits; DDR2 uses 4 bits. Although the effective clock speeds of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became
available.[2]
Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1 leaves off, and is available at clock rates of 400 MHz and higher.
RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets.

MDDR

MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. While standard DDR SDRAM operates at a voltage of 2.5V, MDDR operates at voltage of 1.8V, which allows a reduced power consumption.

See also

★ Dual-channel architecture

★ Serial Presence Detect (SPD)

★ Fully Buffered DIMM

★ List of device bandwidths

★ DDR2 SDRAM, and DDR3 SDRAM which use DDR

★ Double Data Rate

★ Quadruple data rate

External links

★ Official JEDEC website

★ http://www.ddrmemoryram.com/ddrsdram_and_sdram.html

★ http://www.pcguide.com/ref/ram/tech_SDRAM.htm

★ Good guide to Dual Channel DDR

★ Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 Raj Mahajan