I²C

'I²C' is a multi-master serial computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cellphone. The name stands for 'Inter-Integrated Circuit' and is pronounced ''I-squared-C'' and also, incorrectly, ''I-two-C''. As of October 1, 2006, no licensing fees are required to implement the I²C protocol. However, fees are still required in order to obtain I²C slave addresses.[1]

Contents

Design

Reference design

Clock stretching

Arbitration

Physical layer

Timing Diagram

Applications

Operating System Support

Hardware connectivity Solutions - USB and Serial Support

Revisions

Limitations

Derivative Technologies

See also

External links

Design

I²C uses only two bidirectional open-drain lines, Serial Data (SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other, higher or lower, voltages are permitted.
The I²C reference design has a 7-bit address space with 16 reserved addresses, so a maximum of 112 nodes can communicate on the same bus. The most common I²C bus modes are the 100 kbit/s ''standard mode'' and the 10 kbit/s ''low-speed mode'', but clock frequencies down to DC are also allowed. Recent revisions of I²C can host more nodes and run faster (400 kbit/s ''Fast mode'' and 3.4 Mbit/s ''High Speed mode''), and also support other extended features, such as 10-bit addressing.
The maximum number of nodes is obviously limited by the address space, and also by the total bus capacitance of 400 pF.

Reference design

The reference design, as mentioned above, is a bus with a clock (SCL) and data (SDA) lines with 7-bit addressing.
The bus has two types of nodes: master and slave:

★ Master node — node that controls the clock

★ Slave node — node that is not in control of the clock line.
The bus is a multi-master bus which means any number of master nodes can be present.
Additionally, a master can also be a slave, and vice-versa.
Overall, there are four distinct modes of operation for a given bus device:

★ master transmit — the node is in control of the clock and is sending data to a slave

★ master receive — the node is in control of the clock but is receiving data from a slave

★ slave transmit — the node is not in control of the clock but is sending data to a master

★ slave receive — the node is not in control of the clock and is receiving data from the master
The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write to or read from the slave.
If the slave exists on the bus then it will respond with an ACK bit (acknowledge).
The address and the data bytes are sent most significant bit first.
The start bit is indicated by a high->low transition of SDA with SCL high; the stop bit is indicated by a low->high transition of SDA with SCL high.
If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit and the slave is in slave receive mode.)
If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ack bit after every byte but the last one.
The master then ends transmission with a stop bit or can send a START bit, instead, if it wishes to retain control of the bus for another transfer.

Clock stretching

One of the more advanced features of the I²C protocol is clock stretching. An addressed slave device may hold the clock line low after receiving a bit, indicating that it is not ready to process more data. The master that is communicating with the slave will attempt to raise the clock to send out the next bit, but must verify that the clock line was actually raised - if the slave is clock stretching, the clock line will still be low (because the connections are open-drain).
Clock stretching allows slaves that cannot keep up with a master to control the flow of incoming data. Some masters, such as those found inside custom ASICs may not support clock stretching; often times these devices will be labeled as a "two-wire interface" and not strict I²C.

Arbitration

If two masters attempt to get on the bus at the exact same time, arbitration must occur. In contrast to other protocols (such as Ethernet) which use random back-off delays before issuing a retry, I²C has an official arbitration policy. As a master clocks out a slave's address, it must verify after each bit that the SDA line entered the correct state. Thus if one master attempts to write a 1, and at the same instant another master attempts to write a 0, the 0 will pull SDA to ground and the 1 will have no effect. The masters then examine the line, and the master that wrote the 1 realizes that another master is on the bus, and waits for a "stop" bit before trying again.
Arbitration occurs very rarely, but is necessary for proper multi-master support. As with clock-stretching, not all devices support arbitration. Those that do generally label themselves as supporting "multi-master" communication.

Physical layer

At the physical layer, both SCL & SDA lines are of open-drain design, thus, pull-up resistors are needed.
Pulling the line to ground is considered a logical zero while letting the line float is a logical one.
This is used as a channel access method.
When one node is transmitting a logical one (i.e., letting the line float to Vdd) and another transmits a logical zero then the first node can sense this because the line is not in a logical one state — it is not pulled up to Vdd. On SDA, this can be used for arbitration for I²C since it is a multi-master bus; when the address that's read back isn't what was written, one master drops out in favor of another master.
Slaves may also use this on SCL to slow down the clock from the master.
In some systems, slaves also use this mechanism on SDA to arbitrate which of many slaves will respond to a given request from the master.

Timing Diagram

Data transfer is initiated with the START bit ('S') when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green). When the transfer is complete, a STOP bit ('P') is sent by releasing the data line to allow it to be pulled up while SCL is constantly high.

Applications

I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the I²C bus are:

★ Reading configuration data from EEPROMS on DDR2 SDRAM memory sticks and other stacked PC boards

★ Accessing NVRAM chips that keep user settings.

★ Accessing low speed DACs.

★ Accessing low speed ADCs.

★ Changing contrast, hue, and color balance settings in monitors (Display Data Channel).

★ Changing sound volume in intelligent speakers.

★ Controlling OLED/LCD displays, like in a cellphone.

★ Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed.

★ Reading real time clocks.

★ Turning on and turning off the power supply of system components.
A particular strength of I²C is that a microcontroller can control a network of device chips with just two general-purpose I/O pins and software.
Peripherals can also be added to or removed from the I²C bus while the system is running, which makes it ideal for applications that require hot swapping of components.
Buses like I²C became popular when computer engineers realized that much of the manufacturing cost of an integrated circuit design results from its package size and pin count. A smaller package also usually weighs less and consumes less power, which is especially important in cellphones and portable computing.

Operating System Support

In Linux, I²C is handled with a specific kernel module for the specific device. Details on how to write I²C client can be found in the kernel-related documentation and in the /usr/include/linux/i2c.h header file.
OpenBSD has recently added an I²C framework, with support for a number of common master controllers and sensors.
In Sinclair QDOS and Minerva QL operating systems I²C is supported via a set of extensions provided by TF Services.
In AmigaOS the shared library ''i2c.library'' of Wilhelm Noeker allows I²C access.
eCos supports I²C for several hardware architectures.

Hardware connectivity Solutions - USB and Serial Support

There are a number of hardware solutions to give desktop PCs, running Linux, Mac or Windows, I²C master and/or slave capabilities. Most of them are based on Universal Serial Bus (USB) to I²C adaptors. Not all of them require proprietary drivers or APIs.

USB to I²C adaptor project	I2C Modes	Owner	OS Supported
USB I2C/IO Interface Board	Master,Multimaster	DeVaSys	Windows
U2C-12 USB-I2C/SPI/GPIO Interface Adapter	Master	Dimax	Linux,Windows,Mac
Aardvark I2C/SPI Host Adapter	Master,Multimaster,Slave	Totalphase	Linux,Windows
I2C-Tiny-USB	Master	Open Source + Hardware	Linux,Windows,Mac
	Master/Slave	WINI2C + Hardware	Windows
USB-I2C	Master	Devantech	Linux,Windows,Mac,OpenBSD

Serial to I²C bridges are also available, for systems with no USB ports.

Revisions

The original I²C system was created in the early 1980s as a simple internal bus system for building control electronics with various Philips chips.
In 1992 the first standardized version was released, which added a new ''fast mode'' at 400 kbit/s and a 10-bit addressing mode to increase capacity to 1008 nodes. Version 2.0 from 1998 added ''high-speed mode'' at 3.4 Mbit/s with reduced voltage and current requirements that saved power. Version 2.1 from 2001 is a minor cleanup of version 2.0 and is the latest standard.

Limitations

The assignment of slave addresses is one weakness of I²C. Most slaves do not have an independent configuration mechanism and manufacturers rarely dedicate 7 pins to set the slave address. Often, the manufacturer provides pins to configure a few low order bits of the address and arbitrarily sets the higher order bits to some value based on the model, not a vendor ID like other technologies. This limits the number of devices using the same high order bits which may be present on the same bus to some low number, typically between two and eight. Other bus layouts like SPI get around this limitation with individual chip select lines, which then requires that the master use an extra pin for each device or an additional external demultiplexing chip.
The addition of ten-bit addresses to I²C hasn't really caught on yet.
I²C supports a limited range of speeds. At the high end, insufficient bandwidth may be available, while at the low end can cause problems for I²C masters implemented in software (which may become busy) instead of dedicated hardware. All devices must at least partially support the highest speed used or they may spuriously detect their device address.
Once a device has been addressed, it is allowed to slow the clock down to suit its particular needs.

Derivative Technologies

I²C is the basis for the ACCESS.bus, the VESA Display Data Channel (DDC) interface, the System Management Bus (SMBus), and the Intelligent Platform Management Bus (IPMB, one of the protocols of IPMI). These implementations have differences in voltage and clock frequency ranges, and may have interrupt lines.
TWI (Two Wire Interface) is essentially the same bus implemented on various system-on-chip processors from Atmel and other vendors. [2] Vendors use the name TWI due to trademark licensing issues. (Patents on I²C have now lapsed.)

See also

★ I²S

★ 1-Wire Bus

★ Serial Peripheral Interface Bus

★ System Management Bus

★ Serial Presence Detect

External links

★ NXP (formerly Philips) I²C specifications

★ Detailed introduction, Primer

★ Introduction to I²C

★ I²C Bus / Access Bus

★ Using the I²C Bus with Linux

★ OpenBSD iic(4) manual page

★ Linux package lm-sensors supports I²C bus, among others.

★ massmind I²C page Source code, samples and technical information for using I²C with PC, PIC and SX microcontrollers.

★ I²C bus

★ Serial buses information page

★ I²C Bus Technical Overview and Frequently Asked Questions

★ The I²C Faq Version 2.0

★ The Bus Buffer Resource. For 2-wire buses such as I²C, SMBus, PMBus, IPMB & IPMI

★ I²C Licensing Information