INSTRUCTION CYCLE

The '''instruction cycle''' (also called 'fetch-and-execute cycle', 'fetch-decode-execute cycle' ('FDX') can refer to either the time period during which one instruction is fetched from memory and executed when a computer receives a machine language instruction; or the sequence of actions that a CPU performs to execute each machine code instruction in a program.
The name is quite literal. The instruction, along with any data to be worked on, must be 'fetched' from main memory, and then 'executed' by the CPU. A more detailed look at the process is available below.

Contents

Instruction cycle

Fetch the instruction from main memory

Decode the instruction

Fetch data from main memory

Execute the instruction

Store results

Fetch cycle

Execute cycle

Instruction cycle

There are different cycles with complex instruction sets that typically utilize five stages:
Each CPU has different cycles based on different instruction sets. Typically they utilize the following 5 stage Cycle.

Fetch the instruction from main memory

The CPU presents the value of the program counter (PC) on the address bus. The CPU then fetches the instruction from main memory via the data bus into the Memory Data Register (MDR). The value from the MDR is then placed into the Current Instruction Register (CIR), a circuit that holds the instruction so that it can be decoded and executed.

Decode the instruction

The instruction decoder (ID) interprets and implements the instruction.

Fetch data from main memory

Read the effective address from main memory if the instruction has an indirect address. Fetch required data from main memory to be processed and placed into registers.

Execute the instruction

From the instruction register, the data forming the instruction is decoded by the control unit. It then passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the Arithmetic logic unit (ALU) to add them together and writing the result back to a register. A condition signal is sent back to the control unit by the ALU if it is involved.

Store results

The result generated by the operation is stored in the main memory, or sent to an output device. Based on the condition feedback from the ALU, the PC is either incremented to address the next instruction or updated to a different address where the next instruction will be fetched. The cycle is then repeated.

Fetch cycle

Steps 1 and 2 of the Instruction Cycle are called the Fetch Cycle. These steps are the same for each instruction.

Execute cycle

Steps 3 and 4 of the Instruction Cycle are part of the Execute Cycle. These steps will change with each instruction.
The first step of the execute cycle is the Process-Memory. Data is transferred between the CPU and the I/O module. Next is the Data-Processing uses mathematical operations as well as logical operations in reference to data. Central alterations is the next step, is a sequence of operations, for example a jump operation. The last step is a combined operation from all the other steps.