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EspañolINTEL HUB ARCHITECTURE
'Intel Hub Architecture' is Intel's architecture for the 8xx family of chipsets, starting with the Intel 810. It uses a memory controller hub (MCH) that is connected to an I/O Controller Hub (ICH) via a 266 MB/s bus. This connection is sometimes called Direct Media Interface (DMI). The MCH chip supports memory and AGP, while the ICH chip provides connectivity for PCI, USB, sound, IDE hard disks and LAN.
Because of the high-speed channel between the sections, the Intel Hub Architecture (IHA) is much faster than the earlier Northbridge/Southbridge design, which hooked all low-speed ports to the PCI bus. The IHA also optimizes data transfer based on data type.
'Intel Hub Interface 2.0' is currently employed in Intel's line of E7xxx server chipsets. This new revision allows for dedicated data paths for transferring greater than 1.0 GB/s of data to and from the MCH, which support I/O segments with greater reliability and faster access to high-speed networks.
★ First Intel chipset to use IHA
Because of the high-speed channel between the sections, the Intel Hub Architecture (IHA) is much faster than the earlier Northbridge/Southbridge design, which hooked all low-speed ports to the PCI bus. The IHA also optimizes data transfer based on data type.
| Contents |
| Next Generation |
| External links |
Next Generation
'Intel Hub Interface 2.0' is currently employed in Intel's line of E7xxx server chipsets. This new revision allows for dedicated data paths for transferring greater than 1.0 GB/s of data to and from the MCH, which support I/O segments with greater reliability and faster access to high-speed networks.
External links
★ First Intel chipset to use IHA
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