WAFER (ELECTRONICS)

In microelectronics, a 'wafer' is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed by doping (for example, diffusion or ion implantation), chemical etching, and deposition of various materials. Wafers are thus of key importance in the fabrication of semiconductor devices such as integrated circuits.
They are made in various sizes ranging from 1 inch (25.4 mm) to 11.8 inches (300 mm), and thicknesses of the order of 0.5 mm. Generally, they are cut from a boule of semiconductor using a diamond blade or diamond wire, then polished on one or both faces.
Wafers under 200 mm generally have ''flats'' indicating crystallographic planes of high symmetry (usually the {110} face) and, in old-fashioned wafers (those below about 100 mm diameter), the wafer's orientation and doping type (see illustration for conventions). Modern wafers use a notch to convey this information, in order to waste less material [1].
Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. For instance, wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

Contents

Wafer testing

See also

Sources

Wafer testing

Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Sort (WS), Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.
When all test patterns pass for a specific die, its position is remembered for later use during IC packaging. Sometimes a die has internal spare resources available for repairing (i.e. flash memory IC); if it does not pass some test patterns these spare resources can be used. If redundancy of failed die is not possible the die is considered faulty and is thrown away. Non-passing circuits are typically marked with a small dot of ink in the middle of the die, or the information of passing/non-passing is stored in a file, named a wafermap. This map categorizes the passing and non-passing dies by making use of bins. A bin is then defined as a good or bad die. This wafermap is then send by a network or floppy disk to the die attachment process which then only picks up the passing circuits by selecting the bin number of good dies. The process where no ink dot is used to mark the bad dies is named substrate mapping. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot.
In some very specific cases, a die that passes some but not all test patterns can still be used as a product, typically with limited functionality. The most common example of this is a microprocessor for which only one part of the on-die cache memory is functional. In this case, the processor can sometimes still be sold as a lower cost part with a smaller amount of memory and thus lower performance. Additionally when bad dies have has been identified, the die from the bad bin can be used by production personnel for assembly line setup.
The contents of all test patterns and the sequence by which they are applied to an integrated circuit are called the test program.
After IC packaging, a packaged chip will be tested again during the IC testing phase, usually with the same or very similar test patterns. For this reason, one might think that wafer testing is an unnecessary, redundant step. In reality this is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when the production yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and dies will undergo blind assembly.

See also

★ Cobilt

★ Wafer prober

Sources

# A website with semiconductor lore.
# Federal Standard 1037C